[SPIRV] Added support for the constrained arithmetic intrinsic #157441

SubashBoopathi · 2025-09-08T12:38:36Z

Added SPIR-V support for constrained arithmetic intrinsic fmuladd, with legalization, instruction selection, and tests; lowered as a sequence of OpFMul and OpFAdd, consistent with the SPIR-V translator.

github-actions · 2025-09-08T12:39:00Z

Thank you for submitting a Pull Request (PR) to the LLVM Project!

This PR will be automatically labeled and the relevant teams will be notified.

If you wish to, you can add reviewers by using the "Reviewers" section on this page.

If this is not working for you, it is probably because you do not have write permissions for the repository. In which case you can instead tag reviewers by name in a comment by using @ followed by their GitHub username.

If you have received no comments on your PR for a week, you can request a review by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate is once a week. Please remember that you are asking for valuable time from other developers.

If you have further questions, they may be answered by the LLVM GitHub User Guide.

You can also ask questions in a comment on this PR, on the LLVM Discord or on the forums.

llvmbot · 2025-09-08T12:39:29Z

@llvm/pr-subscribers-backend-spir-v

@llvm/pr-subscribers-llvm-globalisel

Author: Subash B (SubashBoopathi)

Changes

Added SPIR-V support for constrained arithmetic intrinsic fmuladd, with legalization, instruction selection, and tests; lowered as a sequence of OpFMul and OpFAdd, consistent with the SPIR-V translator.

Full diff: https://github.com/llvm/llvm-project/pull/157441.diff

6 Files Affected:

(modified) llvm/include/llvm/Support/TargetOpcodes.def (+1)
(modified) llvm/include/llvm/Target/GenericOpcodes.td (+1)
(modified) llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp (+2)
(modified) llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp (+48)
(modified) llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp (+1-1)
(modified) llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll (+4)

diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index b905576b61791..dcf80c56c47b3 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -643,6 +643,7 @@ HANDLE_TARGET_OPCODE(G_FMA)
 
 /// Generic FP multiply and add. Behaves as separate fmul and fadd.
 HANDLE_TARGET_OPCODE(G_FMAD)
+HANDLE_TARGET_OPCODE(G_STRICT_FMULADD)
 
 /// Generic FP division.
 HANDLE_TARGET_OPCODE(G_FDIV)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index ce4750db88c9a..08fbd2253edf2 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1716,6 +1716,7 @@ def G_STRICT_FREM : ConstrainedInstruction<G_FREM>;
 def G_STRICT_FMA : ConstrainedInstruction<G_FMA>;
 def G_STRICT_FSQRT : ConstrainedInstruction<G_FSQRT>;
 def G_STRICT_FLDEXP : ConstrainedInstruction<G_FLDEXP>;
+def G_STRICT_FMULADD : ConstrainedInstruction<G_FMAD>;
 
 //------------------------------------------------------------------------------
 // Memory intrinsics
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index d7280eaba2440..3742df2f1732b 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2061,6 +2061,8 @@ static unsigned getConstrainedOpcode(Intrinsic::ID ID) {
     return TargetOpcode::G_STRICT_FSQRT;
   case Intrinsic::experimental_constrained_ldexp:
     return TargetOpcode::G_STRICT_FLDEXP;
+  case Intrinsic::experimental_constrained_fmuladd:
+    return TargetOpcode::G_STRICT_FMULADD;
   default:
     return 0;
   }
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 6608b3f2cbefd..9d56c18f1c096 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -227,6 +227,9 @@ class SPIRVInstructionSelector : public InstructionSelector {
   bool selectExt(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
                  bool IsSigned) const;
 
+  bool selectStrictFMulAdd(Register ResVReg, const SPIRVType *ResType,
+                           MachineInstr &I) const;
+
   bool selectTrunc(Register ResVReg, const SPIRVType *ResType,
                    MachineInstr &I) const;
 
@@ -689,6 +692,9 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
   case TargetOpcode::G_FMA:
     return selectExtInst(ResVReg, ResType, I, CL::fma, GL::Fma);
 
+  case TargetOpcode::G_STRICT_FMULADD:
+    return selectStrictFMulAdd(ResVReg, ResType, I);
+
   case TargetOpcode::G_STRICT_FLDEXP:
     return selectExtInst(ResVReg, ResType, I, CL::ldexp);
 
@@ -1038,6 +1044,48 @@ bool SPIRVInstructionSelector::selectOpWithSrcs(Register ResVReg,
   return MIB.constrainAllUses(TII, TRI, RBI);
 }
 
+bool SPIRVInstructionSelector::selectStrictFMulAdd(Register ResVReg,
+                                                   const SPIRVType *ResType,
+                                                   MachineInstr &I) const {
+  assert(I.getNumOperands() == 4 &&
+         "FMulAdd should have 3 operands and result");
+  assert(I.getOperand(1).isReg() && I.getOperand(2).isReg() &&
+         I.getOperand(3).isReg() && "Operands should be registers");
+  MachineBasicBlock &BB = *I.getParent();
+  Register MulLHS = I.getOperand(1).getReg();
+  Register MulRHS = I.getOperand(2).getReg();
+  Register AddRHS = I.getOperand(3).getReg();
+  SPIRVType *MulLHSType = GR.getSPIRVTypeForVReg(MulLHS);
+  SPIRVType *MulRHSType = GR.getSPIRVTypeForVReg(MulRHS);
+  SPIRVType *AddRHSType = GR.getSPIRVTypeForVReg(AddRHS);
+  if (!MulLHSType || !MulRHSType || !AddRHSType)
+    report_fatal_error("Input Type could not be determined.");
+  if (!GR.isScalarOrVectorOfType(MulLHS, SPIRV::OpTypeFloat) ||
+      !GR.isScalarOrVectorOfType(MulRHS, SPIRV::OpTypeFloat) ||
+      !GR.isScalarOrVectorOfType(AddRHS, SPIRV::OpTypeFloat)) {
+    report_fatal_error("FMulAdd requires floating-point operands");
+  }
+  bool IsScalar = (MulLHSType->getOpcode() == SPIRV::OpTypeFloat);
+  bool IsVector = (MulLHSType->getOpcode() == SPIRV::OpTypeVector);
+  if (!IsScalar && !IsVector)
+    report_fatal_error("Unsupported type for FMulAdd operation");
+  unsigned MulOpcode = IsScalar ? SPIRV::OpFMulS : SPIRV::OpFMulV;
+  unsigned AddOpcode = IsScalar ? SPIRV::OpFAddS : SPIRV::OpFAddV;
+  Register MulTemp = MRI->createVirtualRegister(MRI->getRegClass(MulLHS));
+  BuildMI(BB, I, I.getDebugLoc(), TII.get(MulOpcode))
+      .addDef(MulTemp)
+      .addUse(GR.getSPIRVTypeID(ResType))
+      .addUse(MulLHS)
+      .addUse(MulRHS)
+      .constrainAllUses(TII, TRI, RBI);
+  return BuildMI(BB, I, I.getDebugLoc(), TII.get(AddOpcode))
+      .addDef(ResVReg)
+      .addUse(GR.getSPIRVTypeID(ResType))
+      .addUse(MulTemp)
+      .addUse(AddRHS)
+      .constrainAllUses(TII, TRI, RBI);
+}
+
 bool SPIRVInstructionSelector::selectUnOp(Register ResVReg,
                                           const SPIRVType *ResType,
                                           MachineInstr &I,
diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
index 721f64a329d31..8041ef67cfa56 100644
--- a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
@@ -193,7 +193,7 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
       .legalFor(allIntScalarsAndVectors)
       .legalIf(extendedScalarsAndVectors);
 
-  getActionDefinitionsBuilder({G_FMA, G_STRICT_FMA})
+  getActionDefinitionsBuilder({G_FMA, G_STRICT_FMA, G_STRICT_FMULADD})
       .legalFor(allFloatScalarsAndVectors);
 
   getActionDefinitionsBuilder(G_STRICT_FLDEXP)
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
index 11bedfa605f9b..b2b8bbfce7321 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
@@ -7,6 +7,7 @@
 ; CHECK-DAG: OpName %[[#r4:]] "r4"
 ; CHECK-DAG: OpName %[[#r5:]] "r5"
 ; CHECK-DAG: OpName %[[#r6:]] "r6"
+; CHECK-DAG: OpName %[[#r7:]] "r7"
 
 ; CHECK-NOT: OpDecorate %[[#r5]] FPRoundingMode
 ; CHECK-NOT: OpDecorate %[[#r6]] FPRoundingMode
@@ -22,6 +23,8 @@
 ; CHECK: OpFMul %[[#]] %[[#]]
 ; CHECK: OpExtInst %[[#]] %[[#]] fma %[[#]] %[[#]] %[[#]]
 ; CHECK: OpFRem
+; CHECK: OpFMul %[[#]] %[[#]]
+; CHECK: OpFAdd %[[#]] %[[#]]
 
 ; Function Attrs: norecurse nounwind strictfp
 define dso_local spir_kernel void @test(float %a, i32 %in, i32 %ui) {
@@ -32,6 +35,7 @@ entry:
   %r4 = tail call float @llvm.experimental.constrained.fmul.f32(float %a, float %a, metadata !"round.downward", metadata !"fpexcept.strict")
   %r5 = tail call float @llvm.experimental.constrained.fma.f32(float %a, float %a, float %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
   %r6 = tail call float @llvm.experimental.constrained.frem.f32(float %a, float %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
+  %r7 = tail call float @llvm.experimental.constrained.fmuladd.f32(float %a, float %a, float %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret void
 }

llvmbot · 2025-09-08T12:39:29Z

@llvm/pr-subscribers-llvm-support

Author: Subash B (SubashBoopathi)

Changes

Added SPIR-V support for constrained arithmetic intrinsic fmuladd, with legalization, instruction selection, and tests; lowered as a sequence of OpFMul and OpFAdd, consistent with the SPIR-V translator.

Full diff: https://github.com/llvm/llvm-project/pull/157441.diff

6 Files Affected:

(modified) llvm/include/llvm/Support/TargetOpcodes.def (+1)
(modified) llvm/include/llvm/Target/GenericOpcodes.td (+1)
(modified) llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp (+2)
(modified) llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp (+48)
(modified) llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp (+1-1)
(modified) llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll (+4)

diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index b905576b61791..dcf80c56c47b3 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -643,6 +643,7 @@ HANDLE_TARGET_OPCODE(G_FMA)
 
 /// Generic FP multiply and add. Behaves as separate fmul and fadd.
 HANDLE_TARGET_OPCODE(G_FMAD)
+HANDLE_TARGET_OPCODE(G_STRICT_FMULADD)
 
 /// Generic FP division.
 HANDLE_TARGET_OPCODE(G_FDIV)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index ce4750db88c9a..08fbd2253edf2 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1716,6 +1716,7 @@ def G_STRICT_FREM : ConstrainedInstruction<G_FREM>;
 def G_STRICT_FMA : ConstrainedInstruction<G_FMA>;
 def G_STRICT_FSQRT : ConstrainedInstruction<G_FSQRT>;
 def G_STRICT_FLDEXP : ConstrainedInstruction<G_FLDEXP>;
+def G_STRICT_FMULADD : ConstrainedInstruction<G_FMAD>;
 
 //------------------------------------------------------------------------------
 // Memory intrinsics
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index d7280eaba2440..3742df2f1732b 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2061,6 +2061,8 @@ static unsigned getConstrainedOpcode(Intrinsic::ID ID) {
     return TargetOpcode::G_STRICT_FSQRT;
   case Intrinsic::experimental_constrained_ldexp:
     return TargetOpcode::G_STRICT_FLDEXP;
+  case Intrinsic::experimental_constrained_fmuladd:
+    return TargetOpcode::G_STRICT_FMULADD;
   default:
     return 0;
   }
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 6608b3f2cbefd..9d56c18f1c096 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -227,6 +227,9 @@ class SPIRVInstructionSelector : public InstructionSelector {
   bool selectExt(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
                  bool IsSigned) const;
 
+  bool selectStrictFMulAdd(Register ResVReg, const SPIRVType *ResType,
+                           MachineInstr &I) const;
+
   bool selectTrunc(Register ResVReg, const SPIRVType *ResType,
                    MachineInstr &I) const;
 
@@ -689,6 +692,9 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
   case TargetOpcode::G_FMA:
     return selectExtInst(ResVReg, ResType, I, CL::fma, GL::Fma);
 
+  case TargetOpcode::G_STRICT_FMULADD:
+    return selectStrictFMulAdd(ResVReg, ResType, I);
+
   case TargetOpcode::G_STRICT_FLDEXP:
     return selectExtInst(ResVReg, ResType, I, CL::ldexp);
 
@@ -1038,6 +1044,48 @@ bool SPIRVInstructionSelector::selectOpWithSrcs(Register ResVReg,
   return MIB.constrainAllUses(TII, TRI, RBI);
 }
 
+bool SPIRVInstructionSelector::selectStrictFMulAdd(Register ResVReg,
+                                                   const SPIRVType *ResType,
+                                                   MachineInstr &I) const {
+  assert(I.getNumOperands() == 4 &&
+         "FMulAdd should have 3 operands and result");
+  assert(I.getOperand(1).isReg() && I.getOperand(2).isReg() &&
+         I.getOperand(3).isReg() && "Operands should be registers");
+  MachineBasicBlock &BB = *I.getParent();
+  Register MulLHS = I.getOperand(1).getReg();
+  Register MulRHS = I.getOperand(2).getReg();
+  Register AddRHS = I.getOperand(3).getReg();
+  SPIRVType *MulLHSType = GR.getSPIRVTypeForVReg(MulLHS);
+  SPIRVType *MulRHSType = GR.getSPIRVTypeForVReg(MulRHS);
+  SPIRVType *AddRHSType = GR.getSPIRVTypeForVReg(AddRHS);
+  if (!MulLHSType || !MulRHSType || !AddRHSType)
+    report_fatal_error("Input Type could not be determined.");
+  if (!GR.isScalarOrVectorOfType(MulLHS, SPIRV::OpTypeFloat) ||
+      !GR.isScalarOrVectorOfType(MulRHS, SPIRV::OpTypeFloat) ||
+      !GR.isScalarOrVectorOfType(AddRHS, SPIRV::OpTypeFloat)) {
+    report_fatal_error("FMulAdd requires floating-point operands");
+  }
+  bool IsScalar = (MulLHSType->getOpcode() == SPIRV::OpTypeFloat);
+  bool IsVector = (MulLHSType->getOpcode() == SPIRV::OpTypeVector);
+  if (!IsScalar && !IsVector)
+    report_fatal_error("Unsupported type for FMulAdd operation");
+  unsigned MulOpcode = IsScalar ? SPIRV::OpFMulS : SPIRV::OpFMulV;
+  unsigned AddOpcode = IsScalar ? SPIRV::OpFAddS : SPIRV::OpFAddV;
+  Register MulTemp = MRI->createVirtualRegister(MRI->getRegClass(MulLHS));
+  BuildMI(BB, I, I.getDebugLoc(), TII.get(MulOpcode))
+      .addDef(MulTemp)
+      .addUse(GR.getSPIRVTypeID(ResType))
+      .addUse(MulLHS)
+      .addUse(MulRHS)
+      .constrainAllUses(TII, TRI, RBI);
+  return BuildMI(BB, I, I.getDebugLoc(), TII.get(AddOpcode))
+      .addDef(ResVReg)
+      .addUse(GR.getSPIRVTypeID(ResType))
+      .addUse(MulTemp)
+      .addUse(AddRHS)
+      .constrainAllUses(TII, TRI, RBI);
+}
+
 bool SPIRVInstructionSelector::selectUnOp(Register ResVReg,
                                           const SPIRVType *ResType,
                                           MachineInstr &I,
diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
index 721f64a329d31..8041ef67cfa56 100644
--- a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
@@ -193,7 +193,7 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
       .legalFor(allIntScalarsAndVectors)
       .legalIf(extendedScalarsAndVectors);
 
-  getActionDefinitionsBuilder({G_FMA, G_STRICT_FMA})
+  getActionDefinitionsBuilder({G_FMA, G_STRICT_FMA, G_STRICT_FMULADD})
       .legalFor(allFloatScalarsAndVectors);
 
   getActionDefinitionsBuilder(G_STRICT_FLDEXP)
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
index 11bedfa605f9b..b2b8bbfce7321 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
@@ -7,6 +7,7 @@
 ; CHECK-DAG: OpName %[[#r4:]] "r4"
 ; CHECK-DAG: OpName %[[#r5:]] "r5"
 ; CHECK-DAG: OpName %[[#r6:]] "r6"
+; CHECK-DAG: OpName %[[#r7:]] "r7"
 
 ; CHECK-NOT: OpDecorate %[[#r5]] FPRoundingMode
 ; CHECK-NOT: OpDecorate %[[#r6]] FPRoundingMode
@@ -22,6 +23,8 @@
 ; CHECK: OpFMul %[[#]] %[[#]]
 ; CHECK: OpExtInst %[[#]] %[[#]] fma %[[#]] %[[#]] %[[#]]
 ; CHECK: OpFRem
+; CHECK: OpFMul %[[#]] %[[#]]
+; CHECK: OpFAdd %[[#]] %[[#]]
 
 ; Function Attrs: norecurse nounwind strictfp
 define dso_local spir_kernel void @test(float %a, i32 %in, i32 %ui) {
@@ -32,6 +35,7 @@ entry:
   %r4 = tail call float @llvm.experimental.constrained.fmul.f32(float %a, float %a, metadata !"round.downward", metadata !"fpexcept.strict")
   %r5 = tail call float @llvm.experimental.constrained.fma.f32(float %a, float %a, float %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
   %r6 = tail call float @llvm.experimental.constrained.frem.f32(float %a, float %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
+  %r7 = tail call float @llvm.experimental.constrained.fmuladd.f32(float %a, float %a, float %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret void
 }

arsenm

Title should be more specific about which intrinsic

arsenm · 2025-09-08T13:00:32Z

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

This function is asserting too many things that should be verifier errors

Okay @arsenm , understood. I’ve removed the unnecessary assert statements and cleaned up the function so it just generates the SPIR-V instructions for fmuladd.

arsenm · 2025-09-08T13:01:03Z

llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll

This style of test is annoying to maintain, have one case per function. Also test more types, like vectors

Okay @arsenm , understood. I’ve created a new dedicated test file for constrained fmuladd, with one case per function, and added coverage for more scalar and vector types.

Gentle reminder @arsenm any updates on this PR?

arsenm

This shouldn't need the fmuladd opcode

arsenm · 2025-10-10T07:22:42Z

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

  return MIB.constrainAllUses(TII, TRI, RBI);
 }

+bool SPIRVInstructionSelector::selectStrictFMulAdd(Register ResVReg,


In this case there's no value in reporting it as legal. I'd expect to just use .lower() and have it break into the separate operations

I’ve updated the implementation to remove the legalization and instead use .lower() for G_STRICT_FMAD, allowing it to break down into separate multiply and add operations as suggested.

arsenm · 2025-10-10T07:23:22Z

llvm/include/llvm/Support/TargetOpcodes.def


 /// Generic FP multiply and add. Behaves as separate fmul and fadd.
 HANDLE_TARGET_OPCODE(G_FMAD)
+HANDLE_TARGET_OPCODE(G_STRICT_FMULADD)


SelectionDAG does not have an equivalent operation. fmuladd is an IR-only construct (there's another PR to add it, but it wouldn't apply in this situation)

My current approach of handling the constrained fmuladd by lowering it into separate fmul and fadd instructions (using .lower()) should be sufficient, right? Or would you suggest a different handling for this case?

arsenm · 2025-10-10T07:23:48Z

llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp

      .legalIf(extendedScalarsAndVectors);

-  getActionDefinitionsBuilder({G_FMA, G_STRICT_FMA})
+  getActionDefinitionsBuilder({G_FMA, G_STRICT_FMA, G_STRICT_FMULADD})


This should be lowered

I’ve updated the implementation to lower G_STRICT_FMAD instead of marking it as legal

github-actions · 2025-10-13T03:56:27Z

✅ With the latest revision this PR passed the C/C++ code formatter.

s-perron · 2025-11-10T18:41:48Z

llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp

If the G_STRICT_FMAD is applied to a float or vector of floats, it will not be lowered. Is that what you want?

If you want it lowered all of the time, remove this line. I expect that is what you want based on earlier PRs.

@s-perron I understood and I modified the legalizer info to directly lower the intrinsic as expected.

llvmbot added llvm:globalisel backend:SPIR-V llvm:support labels Sep 8, 2025

arsenm reviewed Sep 8, 2025

View reviewed changes

SubashBoopathi force-pushed the constrained_fmuladd branch from 2e42a7d to b2c1390 Compare September 9, 2025 05:50

Added Support for the Constrained fmuladd

d512507

michalpaszkowski requested a review from arsenm September 28, 2025 23:39

arsenm requested changes Oct 10, 2025

View reviewed changes

Removed the legalization of the Opcode and used lower()

61dad88

SubashBoopathi force-pushed the constrained_fmuladd branch from c6de1d1 to 61dad88 Compare October 13, 2025 03:52

Slight changes in the format of legalizerinfo

082c8aa

MrSidims requested review from Keenuts, MrSidims, arsenm, michalpaszkowski and s-perron November 5, 2025 15:06

s-perron reviewed Nov 10, 2025

View reviewed changes

Modified the legalization conditions to lower the instruction directly

b9d3905

[SPIRV] Added support for the constrained arithmetic intrinsic #157441

Are you sure you want to change the base?

[SPIRV] Added support for the constrained arithmetic intrinsic #157441

Conversation

SubashBoopathi commented Sep 8, 2025

Uh oh!

github-actions bot commented Sep 8, 2025

Uh oh!

llvmbot commented Sep 8, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

llvmbot commented Sep 8, 2025

Uh oh!

arsenm left a comment

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

arsenm left a comment

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

github-actions bot commented Oct 13, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

4 participants

llvmbot commented Sep 8, 2025 •

edited

Loading

github-actions bot commented Oct 13, 2025 •

edited

Loading